On May 2021, Syed Rashid presented, at Vortex-CoLab, the work he has developed in his Ph.D. about bounding the contention due to sharing of hardware resources in multicore processors.

Nowadays, multi-core processors have become mainstream and are used across several domains. However, due to the unpredictable nature of these multi-core processors, their use in time-critical applications, that require absolute timing guarantees, is very restrictive. Nondeterminism and unpredictability exist in multi-core platforms, due to the use of shared resources such as cache and interconnects. In his work, Syed Rashid focuses on bounding the shared cache and interconnecting contention between tasks running on the same or different cores of a multicore processor. The results presented, at this talk, show a significant improvement in the accuracy of the schedulability analysis, by tightening the bounds on inter-task cache and interconnect contention.


About Syed Aftab Rashid:

Syed Aftab Rashid is an Embedded Systems Research Scientist at Vortex-CoLab and serves as an integrated researcher at CISTER Research Unit. He completed his Ph.D. from the University of Porto, Portugal, in 2021. His dissertation was on the timing analysis of multicore platforms for hard real-time systems with a focus on contention due to sharing of cache memories and interconnects. He received his M.Sc. in Electrical Engineering from the National University of Computer and Emerging Sciences (NUCES)-FAST, Islamabad, Pakistan in 2014. He has worked on several international projects related to embedded system design and implementation. His research interests include real-time embedded systems, timing and scheduling analysis, resource contention, and multicore architectures’ predictability.